ADI公司的AD9213是12位10.25 GSPS RF模擬數(shù)轉(zhuǎn)換器（ADC），輸入帶寬6.5GHz，支持需要寬瞬態(tài)帶寬和低代碼誤差速率（CER）的高動態(tài)范圍頻率和時域應(yīng)用.AD9213具有16路JESD204B接口，以支持它的最大帶寬功能。它具有業(yè)界一流的動態(tài)范圍和線性信性能而功耗僅為5.1W（10GSPS取樣），基于交錯管道架構(gòu)，具有專有校準和隨機化技術(shù)，它能抑制交錯雜散信號進固有噪聲電平。噪音頻譜密度為154 dBFS/Hz， SFDR為70 dBc （1 GHz， ?1 dBFS）。器件集成的輸入緩沖器輸入帶寬為6.5GHz，RIN=50Ω時1.4Vp-p滿刻度輸入，集成了數(shù)字下變換器（DDC），主要用在4G/5G 多頻段無線通信基站，多標準生產(chǎn)測試系統(tǒng)和防御電子產(chǎn)品等 GHz 帶寬應(yīng)用。本文介紹了AD9213主要特性，功能框圖，數(shù)字下變換器（DDC）框圖以及高速評估板ADS8-V1EBZ主要特性，電路圖，材料清單和PCB設(shè)計圖。

The AD9213 is a single 12-bit， 10.25 GSPS， RF analog-to-digital converter （ADC） with a 6.5 GHz input bandwidth. The AD9213 has been optimized to support high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low code error rates （CER）。 The AD9213 features a 16-lane JESD204B interface to support its maximum bandwidth capability.

The AD9213 achieves industry leading dynamic range and linearity performance while consuming only 5 W. Based on an interleaved pipeline architecture， the AD9213 features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The excellent linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration resulting in excellent spurious free performance over a wide range of input signal conditions.

Applications requiring less instantaneous bandwidth can benefit from the on-chip digital signal processing （DSP） capability of the AD9213 that reduces the output data rate along with the number of JESD204b lanes required to support it. The DSP path includes a digital downconverter （DDC） with a 48-bit， numerically controlled oscillator （NCO） followed by an I and Q digital decimator stage allowing for selectable decimation rates that are factors of two or three. For fast frequency hopping applications， the AD9213 NCO supports up to 16-profile settings with separate trigger input allowing for wide surveillance frequency coverage but at a reduced JESD204B lane count.

The AD9213 also supports sample accurate multichip synchronization that also includes synchronization of the NCOs. The AD9213 will be offered in a 192 flip-chip ball grid array （FcBGA） package. The AD9213 is specified over a junction temperature range of ?10℃ to +115℃。

AD9213主要特性：

High instantaneous dynamic range

Noise spectral density 154 dBFS/Hz

SFDR 70 dBc （1 GHz， ?1 dBFS）

Low power consumption： 5.1 W at 10 GSPS

Integrated input buffer （6.5 GHz input bandwidth）

1.4 V p-p full-scale input with RIN = 50 Ω

Overvoltage protection

16-lane JESD204B output （up to 16 Gbps line rate）

Multichip sync capable with 1 sample accuracy

DDC NCO synchronization included

Fast overrange detection for efficient AGC

Integrated DDC

Selectable decimation factors

16-profile settings for fast frequency hopping

Optional on-chip PLL clock multiplier

On-chip temperature sensor

On-chip negative voltage generators

Low CER 《1e?16

12 mm × 12 mm BGA

圖1.AD9213功能框圖

圖2.AD9213數(shù)字下變換器（DDC）框圖

圖3. AD9213評估板和ADS8-V1EBZ數(shù)據(jù)捕獲板連接圖

高速評估板ADS8-V1EBZ

The ADS8-V1 Evaluation Board was developed to support the evaluation of Analog Devices High Speed Data Converters with JESD204B bit rates up to 16Gbps. This Wiki site provides a high level overview of the platform. In addition， each use-case of the board has its own section （e.g. Using the ADS8-V1 for High Speed A/D Converter Evaluation）。 The ADS8-V1 is intended to be used only with specified Analog Devices Evaluation Boards. The ADS8-V1 is not intended to be used as a general purpose development platform， and no support is available for standalone operation. The ADS8-V1 may contain hardware features not fully productized or supported by our default customer evaluation configurations. Please refer to Xilinx and its approved distributors for general purpose FPGA Development Kits.

高速評估板ADS8-V1EBZ主要特性：

1. Xilinx KintexUltrascale XCKU040-3FFVA1156E FPGA.

2. One （1） FMC+ connector.

3. Twenty （20） 16Gbps transceivers supported by one （1） FMC+ connector.

4. DDR4 SDRAM.

5. Simple USB 3.0 port interface.

圖4.高速評估板ADS8-V1EBZ外形圖（頂面）

圖5.高速評估板ADS8-V1EBZ外形圖（底面）

When connected to a specified Analog Devices high speed adc evaluation board， the ADS8-V1 works as a data acquistion board. Designed to support the highest speed JESD204B A/D Converters， the FPGA on the ADS8-V1 acts as the data receiver， while the ADC is the data transmitter. A typical test setup is shown below.

圖6.高速評估板ADS8-V1EBZ和高速ADC評估板連接圖

圖7.高速評估板ADS8-V1EBZ電路圖（1）

圖8.高速評估板ADS8-V1EBZ電路圖（2）

圖9.高速評估板ADS8-V1EBZ電路圖（3）

圖10.高速評估板ADS8-V1EBZ電路圖（4）

圖11.高速評估板ADS8-V1EBZ電路圖（5）

圖12.高速評估板ADS8-V1EBZ電路圖（6）

圖13.高速評估板ADS8-V1EBZ電路圖（7）

圖14.高速評估板ADS8-V1EBZ電路圖（8）

圖15.高速評估板ADS8-V1EBZ電路圖（9）

圖16.高速評估板ADS8-V1EBZ電路圖（10）

圖17.高速評估板ADS8-V1EBZ電路圖（11）

圖18.高速評估板ADS8-V1EBZ電路圖（12）

圖19.高速評估板ADS8-V1EBZ電路圖（13）

圖20.高速評估板ADS8-V1EBZ電路圖（14）

圖21.高速評估板ADS8-V1EBZ電路圖（15）

圖22.高速評估板ADS8-V1EBZ電路圖（16）

圖23.高速評估板ADS8-V1EBZ電路圖（17）

圖24.高速評估板ADS8-V1EBZ電路圖（18）

圖25.高速評估板ADS8-V1EBZ電路圖（19）

圖26.高速評估板ADS8-V1EBZ電路圖（20）

圖27.高速評估板ADS8-V1EBZ電路圖（21）

圖28.高速評估板ADS8-V1EBZ電路圖（22）

圖29.高速評估板ADS8-V1EBZ電路圖（23）

圖30.高速評估板ADS8-V1EBZ電路圖（24）

圖31.高速評估板ADS8-V1EBZ電路圖（25）

圖32.高速評估板ADS8-V1EBZ電路圖（26）

圖33.高速評估板ADS8-V1EBZ PCB設(shè)計圖（1）

圖34.高速評估板ADS8-V1EBZ PCB設(shè)計圖（2）