The fast trend towards digital processing of analogue signals in an increased number of application fields has stimulated significant research efforts in the area of data converters implemented in CMOS technologies. High-speed high-resolution Analogue-to-Digital Converters (ADCs) are required in the front-end receive paths of many modern communication systems. For input signal bandwidths larger than a few MHz, self-calibrated pipelined solutions show speed and power advantages when compared to other architectures.
The work reported in this Book comprises two major research areas in
the field of high-speed self-calibrated pipelined ADCs. The first area covers
the study and the successful implementation of a novel analogue selfcalibration
technique required to extend the limited linearity of front-end stages in pipelined Analogue-to-Digital (A/D) converters, since component fabrication accuracy is limited and rarely stable or well characterised during the useful life of any process. The second area comprises the development of a systematic design methodology for the optimisation of high-speed selfcalibrated pipelined A/D converters that takes into account physical limitations for practical integrated circuit implementations, including thermal noise and component matching accuracy. It is demonstrated that multi-bit, rather than single-bit resolution-per-stage architectures have to be considered for optimising the resulting silicon area and power dissipation.
Several practical realisations with consistent measured results clearly
assess the feasibility of the proposed self-calibration technique, validate the
main theoretical findings and demonstrate the attractiveness in terms of
power dissipation and reduced die area of the established design methodology.
This book is organised in seven Chapters. In the first one, the
introduction, the motivation that has originated this research work is
presented and the main original goals are also pointed out.
In the second Chapter an important set of widely used performance
parameters for Nyquist ADCs is presented. The main sources of errors and
non-idealities in pipelined ADCs are described next. For a better
understanding of the fundamental limits of this type of architecture as well
as solutions commonly used to overcome these limitations are also addressed
in this Chapter. Finally, at the end of Chapter two, existing relevant works in
pipelined A/D converters are listed and compared in terms of performance
versus power dissipation and occupied silicon area by means of commonly
used figures of merit.
The third Chapter describes an efficient analogue code-by-code selfcalibration
technique to extend the linearity of critical front-end stages of
pipelined A/D converters. In order to prove the feasibility of the proposed
technique, a prototype was designed and fabricated in a current CMOS
technology. Measured results have shown levels of accuracy compatible
with 14 bits of resolution, while allowing input signal bandwidths in the
MHz range. At the end of the Chapter, computer behavioural simulations of
a complete model of a high-resolution pipelined ADC are given to
demonstrate the correct operation as well as the benefits of the proposed
technique.
In the fourth Chapter a systematic design methodology for the optimisation of high-speed pipelined self-calibrated A/D converters is presented. High-speed pipelined analogue-digital converters have been previously considered using optimum 1-bit per stage architectures that typically can attain untrimmed resolution of up to 10 bits. In this Chapter it
is demonstrated that multi-bit, rather than single-bit resolution per stage
architectures have to be considered for optimising the resulting area and
power dissipation whilst minimising stringent requirements of the constituent building blocks. Such optimisation is achieved through a systematic design process that takes into account physical limitations for practical integrated circuit implementation, including thermal noise and component matching accuracy. The impact of the selected pipelined configuration in the self-calibration requirements as well as in the practical feasibility of the active components is analysed. A design example is presented to consolidate the relevant conclusions.
Chapter five presents the design of a complete 14-bit 5MS/s CMOS pipelined A/D converter with an architecture tailored accordingly to the systematic methodology described in Chapter four. This implementation uses the self-calibration technique presented in Chapter three and explores the concept of background calibration. All issues related to the design of the building blocks, testing modes and system level simulations are addressed also in this Chapter.
In Chapter six two practical realisations of CMOS pipelined A/D converters are described, together with the corresponding experimental results. In particular, an integrated 14-bit 5 MS/s background self-calibrated pipelined ADC with low power dissipation and low area is fully described.
Furthermore, layout considerations as well as details of the design of the
measurement setup are also presented.
Finally, Chapter seven draws the relevant conclusions of this book and
proposes new directions for future work.