MM54HC4046/MM74HC4046
CMOS Phase Lock Loop
General Description
The MM54HC4046/MM74HC4046 is a low power phase
lock loop utilizing advanced silicon-gate CMOS technology
to obtain high frequency operation both in the phase comparator
and VCO sections. This device contains a low power
linear voltage controlled oscillator (VCO), a source follower,
and three phase comparators. The three phase comparators
have a common signal input and a common comparator
input. The signal input has a self biasing amplifier allowing
signals to be either capacitively coupled to the phase comparators
with a small signal or directly coupled with standard
input logic levels. This device is similar to the CD4046 except
that the Zener diode of the metal gate CMOS device
has been replaced with a third phase comparator.
Phase Comparator I is an exclusive OR (XOR) gate. It provides
a digital error signal that maintains a 90 phase shift
between the VCO's center frequency and the input signal
(50% duty cycle input waveforms). This phase detector is
more susceptible to locking onto harmonics of the input frequency
than phase comparator I, but provides better noise
rejection.
Phase comparator III is an SR flip-flop gate. It can be used
to provide the phase comparator functions and is similar to
the first comparator in performance.
Phase comparator II is an edge sensitive digital sequential
network. Two signal outputs are provided, a comparator output
and a phase pulse output. The comparator output is a
TRI-STATEé output that provides a signal that locks the
VCO output signal to the input signal with 0 phase shift
between them. This comparator is more susceptible to
noise throwing the loop out of lock, but is less likely to lock
onto harmonics than the other two comparators.
In a typical application any one of the three comparators
feed an external filter network which in turn feeds the VCO
input. This input is a very high impedance CMOS input
which also drives the source follower. The VCO's operating
frequency is set by three external components connected to
the C1A, C1B, R1 and R2 pins. An inhibit pin is provided to
disable the VCO and the source follower, providing a method
of putting the IC in a low power state.
The source follower is a MOS transistor whose gate is connected
to the VCO input and whose drain connects the Demodulator
output. This output normally is used by tying a
resistor from pin 10 to ground, and provides a means of
looking at the VCO input without loading down modifying the
characteristics of the PLL filter.