These 8-bit bus-interface flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The eight flip-flops are edge-triggered D-type flip-flops. With the clock-enable () input low, the device enters data on the low-to-high transition of the clock. Taking high disables the clock buffer, thus latching the outputs. Taking the clear () input low causes the eight Q outputs to go low independently of the clock.

Buffered output-enable (,, or) inputs can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state.