提出了一種基于FPGA并利用Verilog HDL實現(xiàn)的CMI編碼設(shè)計方法。研究了CMI碼型的編碼特點，提出了利用Altera公司CycloneⅡ系列EP2C5Q型號FPGA完成CMI編碼功能的方案。在系統(tǒng)程序設(shè)計中，首先產(chǎn)生m序列，然后程序再對m序列進(jìn)行CMI碼型變換。在CMI碼型變換過程中，采用專用寄存器對1碼的狀態(tài)進(jìn)行了存儲，同時利用m序列的二倍頻為CMI編碼進(jìn)程提供時鐘激勵，最后輸出CMI碼型。實驗結(jié)果表明，采用FPGA完成CMI編碼的設(shè)計，編碼結(jié)果完全正確，能夠達(dá)到預(yù)期要求。利用這種方法實現(xiàn)CMI編碼功能，具有效率高、可擴展性強、升級方便等特點，方便嵌入到大規(guī)模設(shè)計中，具有廣泛的應(yīng)用前景。

Abstract:

?In order to implement CMI encoded system, a method based on FPGA and programmed with Verilog HDL is presented. Based on the research of CMI encoded characteristic, EP2C5Q of Altera corporation CycloneⅡ FPGA is used to finish CMI encoded function. In the design of system program, m series were generated at first, then the m series were transformed into CMI code. In the process of CMI encoding, a special register is used to save the state of code 1, at the same time, the clock of CMI encoding process is provided by two times m series’ clock, then the CMI code was output. The experiment results indicate that using the FPGA to implement CMI encoded, the encoded result is completely correct, it can achieve the prospective requirements. This method has the excellent characteristic of high efficiency, extended quality and convenient upgrade, the design is easily embedded into a large system and has wide prospect in practical application.